Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - MAX PLUS II

Search list

[Other resource] CPLDxiaoche

Description: 智能机器小车主要完成寻迹功能，由机械结构和控制单元两个部分组成。机械结构是一个由底盘、前后辅助轮、控制板支架、传感器支架、左右驱动轮、步进电机等组成。控制单元部分主要由主要包含传感器及其调理电路、步进电机及驱动电路、控制器三个部分。本设计的核心为控制器部分，采用Altera MAX7000S系列的EPM7064LC84-15作主控芯片。CPLD芯片的设计主要在MAX+plusⅡ10.0环境下利用VHDL语言编程实现。驱动步进电机电路主要利用ULN2803作为驱动芯片。 -intelligent machines trolley track of the major functions by mechanical structure and control modules of two components. Mechanical structure is a chassis, after supporting wheels, the control panel stent, sensors stent, driving wheel around, Stepper motors, and other components. Some of the main control unit from the mainly contains sensors and conditioning circuits, and stepper motor drive circuit, the controller of three parts. The design for the core controller, Altera MAX7000S the EPM7064LC84-15 for the control chip. CPLD chip design mainly in MAX II plus 10.0 environment using VHDL programming. Stepper motor driver circuit using mainly driven ULN2803 chip.
Platform: | Size: 1369 | Author: lili | Hits:

[Embeded-SCM Develop] EDA12

Description: EDA技术应用.用QUARTUES II 实现EDA技术实验操作,类似于精典的MAX+PLUS
Platform: | Size: 3999277 | Author: 曾伟 | Hits:

[VHDL-FPGA-Verilog] CPLDxiaoche

Description: 智能机器小车主要完成寻迹功能，由机械结构和控制单元两个部分组成。机械结构是一个由底盘、前后辅助轮、控制板支架、传感器支架、左右驱动轮、步进电机等组成。控制单元部分主要由主要包含传感器及其调理电路、步进电机及驱动电路、控制器三个部分。本设计的核心为控制器部分，采用Altera MAX7000S系列的EPM7064LC84-15作主控芯片。CPLD芯片的设计主要在MAX+plusⅡ10.0环境下利用VHDL语言编程实现。驱动步进电机电路主要利用ULN2803作为驱动芯片。 -intelligent machines trolley track of the major functions by mechanical structure and control modules of two components. Mechanical structure is a chassis, after supporting wheels, the control panel stent, sensors stent, driving wheel around, Stepper motors, and other components. Some of the main control unit from the mainly contains sensors and conditioning circuits, and stepper motor drive circuit, the controller of three parts. The design for the core controller, Altera MAX7000S the EPM7064LC84-15 for the control chip. CPLD chip design mainly in MAX II plus 10.0 environment using VHDL programming. Stepper motor driver circuit using mainly driven ULN2803 chip.
Platform: | Size: 1024 | Author: lili | Hits:

[Embeded-SCM Develop] EDA12

Description: EDA技术应用.用QUARTUES II 实现EDA技术实验操作,类似于精典的MAX+PLUS-EDA applications. QUARTUES II with EDA technology to achieve the experimental operation, similar to the classical MAX+ PLUS
Platform: | Size: 3998720 | Author: 曾伟 | Hits:

[VHDL-FPGA-Verilog] decoder_2_10

Description: 采用VHDL语言编写的二-十进制编码器，在MAX+plus软件上实现，其中包括演示截图。-Using VHDL languages II- Decimal encoder, in MAX+ Plus software to achieve, including the demo screenshot.
Platform: | Size: 1793024 | Author: 画眉 | Hits:

[Books] Crack_QII90

Description: 您现在阅读的是 Quartus II 简介手册。 Altera® Quartus® II 设计软件是适合 单芯片可编程系统 (SOPC) 的最全面的设计环境。 如果您以前用过 MAX+PLUS® II 软件、其它设计软件或 ASIC 设计软件，并且准备改用 Quartus II 软件，或如果您对 Quartus II 软件有了一些了解但想进一步了解 它的功能，那么本手册非常适合您。-You are reading the Quartus II brochure. Altera ® Quartus ® II design software is suitable for Single-Chip Programmable System (SOPC) the most comprehensive design environment. If you ve used MAX+ PLUS ® II software, ASIC design software or other design software, and is prepared to use Quartus II software, or if you have some understanding of Quartus II software, but would like to learn more about Its function, then this manual is for you.
Platform: | Size: 29696 | Author: 陈冉 | Hits:

[Other] verilog_hdl

Description: You can now read the brochure in the Quartus II. Altera ® the Quartus ® II design software is suitable for The most comprehensive single-chip programmable system (SOPC) design environment. If you have previously used MAX + PLUS ® II software, and other design software or ASIC design software and are ready to switch Quartus II software, or if you have some understanding of the Quartus II software, but want to learn more Its functions, this manual is for you. -verilog_hdl Language Tutorial
Platform: | Size: 1344512 | Author: 任耀庭 | Hits:

[source in ebook] duogongnengshuzizhong

Description: 南京工程学院 数电课程设计 多功能数字钟 电路图 所有实验文件打包.zip包括做实验的所有文件打包给大家啦，MAX+plus II设计电路图，gdf文件，mod文件，报告书，一切齐全啦，当时被评为优秀成绩的，特别推荐给大家，电路绝对优秀，直接上机操作，导入电路图即可验证演示。-Number of Nanjing Institute of Electrical curriculum design electronic locks files packaged all experiments, including experiments, all files are packaged to give you friends, MAX+ plus II design schematics, gdf files, mod files, reports, everything is complete you, then was named excellent results, especially recommended for everyone, circuit absolutely outstanding, directly on the machine operation, import circuit can verify demonstration.
Platform: | Size: 1475584 | Author: zxy | Hits:

[source in ebook] jiaotongdengkongzidianlu

Description: 南京工程学院 数电课程设计 交通灯控制电路的设计 电路图 所有实验文件打包.zip.zip包括做实验的所有文件打包给大家啦，MAX+plus II设计电路图，gdf文件，mod文件，报告书，一切齐全啦，当时被评为优秀成绩的，特别推荐给大家，电路绝对优秀，直接上机操作，导入电路图即可验证演示。-Nanjing Institute of number of electrical curriculum design traffic light control circuit design schematics all experiments files packaged. Zip.zip experiment all the files, including package to you friends, MAX+ plus II design schematics, gdf files, mod files, reports, all complete it, then was named outstanding achievements, particularly recommended for everyone, circuit absolutely outstanding, directly on the machine operation, import circuit can verify demonstration.
Platform: | Size: 400384 | Author: zxy | Hits:

[VHDL-FPGA-Verilog] music_ic

Description: 此為VHDL之音樂IC設計，透過Max Plus II將設計結果顯示。-This is the music of IC design VHDL, designed by Max Plus II results will be displayed.
Platform: | Size: 405504 | Author: | Hits:

[VHDL-FPGA-Verilog] shi01

Description: FPGA上机文件一所以在FPGA中采用同 步设计非常重要 MAX+PLUS II可以计算出数据传输需要(fpga Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximum allowable Clock frequency)
Platform: | Size: 33792 | Author: coldplay | Hits:
« 1 2 3 4 5»

CodeBus www.codebus.net